Strategic compiler engagement with a leading hardware company building custom RISC-V cores for high-throughput packet and protocol processing. We extend LLVM with backends and optimization passes targeting their proprietary ISA extensions, and design the programming model — framework, library set, and APIs — that lets application developers reach the hardware's full performance from standard C/C++. Quality is held to silicon-grade standards from day one: RTL co-verification, automated regression suites, and continuous integration around every compiler change.
The Challenge
RISC-V is open, but custom RISC-V silicon is not — every networking-class core pairs the base ISA with proprietary instruction extensions for packet parsing, protocol acceleration, and on-die memory operations, and none of it exists in any off-the-shelf compiler. Without a toolchain that understands those extensions, application teams either drop into hand-written assembly or leave most of the hardware's performance on the table; without a programming model on top, even a working compiler cannot be put in the hands of dataplane developers who need to ship features, not learn a new ISA. Our partner — a leading hardware company building custom RISC-V silicon for advanced networking — needed both a production-grade LLVM backend for their architecture and the framework around it that turns custom instructions into something developers can actually use.
Our Approach
We work directly inside LLVM's RISC-V target, adding the instruction definitions, intrinsics, scheduling models, register-allocation adjustments, and codegen patterns that surface the partner's custom extensions to the optimizer and to the developer through clean C/C++ entry points. On top of the compiler, we design a programming model and SDK tuned for packet and protocol processing — a framework, library set, and APIs that abstract pipeline stages, packet I/O, and protocol primitives so application code stays portable while the compiler lowers it onto the custom ISA. Verification runs alongside development from day one: hand-written and randomized test suites exercise every new instruction and optimization pass, RTL co-simulation pins compiler output against the hardware model, and the whole stack runs in continuous integration so every change is regression-checked before it lands. Where it is the right call, we lean on the wider LLVM and RISC-V ecosystem — upstream conventions, sanitizers, fuzzing — rather than reinventing what the community already maintains well.
Results
Application developers write standard C/C++ and get optimized binaries that fully exploit the custom RISC-V instruction set, without ever reaching for assembly. The programming model and SDK keep dataplane code idiomatic and portable across the partner's hardware roadmap, while the verification harness — RTL co-simulation alongside CI-driven regression — lets the toolchain ship changes at hardware-team velocity without trading away correctness. The collaboration extends our long track record on LLVM-based compilers for novel architectures into the RISC-V era, on a platform purpose-built for the next generation of networking silicon.
